Along with the progress of industry of semiconductor field, the feature size of the MOSFET scales down. The result is that more and more devices can be integrated into a same area on a silicon chip, therefore the performance of an integrated circuit is improved and its field of utilization is enlarged.
According to the scaling rule, as the feature size goes down, the thickness of the gate oxide film of the MOSFET decreases. However, dielectric breakdown may be induced by thin gate oxide, which deteriorates the reliability of MOSFET devices.
Conventional process of manufacturing gate oxide of the MOSFET includes the following steps:
First of all, wafers are put into a processing with machine for proceeding the subsequent oxidation procedure, then a gate oxide region pre-cleanning step is performed to get a good oxide interface characteristic. Therefore, gate oxidation could be subsequently performed to form a thin gate oxide film in the approximate range of 100.about.120 .ANG., that could be achieved by letting the wafers be surrounded by wet oxygen (O.sub.2) ambient, and then the following steps are photo resist coating, exposure and development.
After that, a couple times of ion implantation steps are performed, and the subsequent step is photo resist removing. Then a gate oxide post-clean step could be carried out (e.g. SPM clean) for the purpose of good attachment of a gate polysilicon layer in the subsequent step. After the deposition of the gate polysilicon layer, a POCl.sub.3 gas diffusion procedure is carried out for doping the N type (i.e. Phosphorus) ions into the specific region of device, then a deglazing step is performed to remove the surface silicon glass of device, in order to get good attachment of the following coated photoresist. Therefore, the following steps are gate photoresist coating, exposure and development.
Finally, after the gate etching step, two main electrical characteristic tests, (i.e. Ebd and Qbd test) could be performed.
In the conventional process of manufacturing 16M dynamically random access memory (DRAM), there are three times of coating and removing of photo resist, and three times of ion implantation steps are performed to adjust Vtn1, Vtn2, and Vtp. As shown in Table I and Table II, each kind of chemical cleaning step for removing photo resist, including APM, HPM, CDI, SPM, HDI will all deteriorate the performance of the gate oxide since the breakdown voltage of the gate oxide is reduced, and Ebd will shift from C mode to low voltage, therefore the yield of product is low.
TABLE I __________________________________________________________________________ Ebd and Qbd data of each test condition Ebd Pass Rate (%) Qbd Pass Rate (%) Lot ID Wafer ID Condition &gt;8 MV/cm &gt;1 Coul/cm.sup.2 __________________________________________________________________________ LD30092 1 1. Gox120 .ANG./APM 11.54% 7.69% LD30092 2 2. Gox120 .ANG./HPM 17.86% 17.86% LD30092 3 3. Gox120 .ANG./CDI 0.00% 0.00% LD30092 4 4. Gox120 .ANG./SPM 0.00% 0.00% LD30092 5 5. Gox120 .ANG./HDI 0.00% 0.00% LD30091 16 6. Gox120 .ANG. 96.3% 88.89% __________________________________________________________________________
The data listed in table I could further correspond to the result shown in FIG. 1, which clarify the Ebd and Qbd test results processed by using the conventional gate oxidation procedure. It indicates that the gate oxide was deteriorated by APM, HPM, SPM and hot or cold DI rinse on oxide surface from Ebd and Qbd result.
TABLE II __________________________________________________________________________ Qbd result Wafer Average Lot ID ID Condition &gt;1 Coul/cm.sup.2 &gt;10 Coul/cm.sup.2 &gt;15 Coul/cm.sup.2 (Coul/cm.sup.2) __________________________________________________________________________ LD30092 1 1. Gox120 .ANG./APM 6.7% 0.0% 0.0% 0.400 LD30092 2 2. Gox120 .ANG./HPM 40% 13.2% 6.7% 3.200 LD30092 3 3. Gox120 .ANG./CDI 0.0% 0.0% 0.0% 0.001 LD30092 4 4. Gox120 .ANG./SPM 0.0% 0.0% 0.0% 0.001 LD30092 5 5. Gox120 .ANG./HDI 0.0% 0.0% 0.0% 0.001 LD30091 16 6. Gox120 .ANG. 76.7% 60.0% 50.5% 13.400 __________________________________________________________________________
The data shown in TABLE II indicate that gate oxide deteriorates by chemical cleaning. DI water rinse can even deteriorate charge to breakdown of gate oxide to 0%. However, HPM clean shows less degraded effect.